1. Technical Field of the Invention
The present invention relates to power on reset circuits or other circuits configured to generate a one-shot pulse
2. Description of Related Art
Reference is now made to FIG. 1 wherein there is shown a schematic diagram of a prior art power on reset circuit 100. At the heart of the circuit 100 is a latch 102 formed by transistors Q1–Q4. More specifically, p-channel transistors Q1 and Q2 are connected in a cross-coupled relationship wherein the gate of one transistor is connected to the drain of the other transistor. The sources of transistors Q1 and Q2 are connected to Vdd. The gate of transistor Q1 is further connected to Vdd through a capacitor C1, and the gate of transistor Q2 is further connected to ground (GND) through a capacitor C2. The latch 102 further includes a pair of n-channel transistors Q3 and Q4. The drain of transistor Q3 is connected to the drain of transistor Q1 at a first latched node 104 of the latch 102, while the source of transistor Q3 is connected to ground. The drain of transistor Q4 is connected to the drain of transistor Q2 at a second latched node 106 of the latch 102, while the source of transistor Q4 is connected to ground. The gates of transistors Q1 and Q3 are connected together and to the second latched node 106. The gates of transistors Q2 and Q4 are connected together and to the first latched node 104.
The circuit 100 further includes a p-channel transistor Q5 and an n-channel transistor Q6 source-drain connected in series between Vdd and ground. The gate of transistor Q5 is connected to a feedback node 120 and is further connected to Vdd through a capacitor C3, while the gate of transistor Q6 is connected to Vdd
The connected drains of transistors Q5 and Q6 are connected at an input node 122 to the gate of n-channel transistor Q7 and are further connected to ground through a capacitor C4. The source of transistor Q7 is connected to ground, and the drain of transistor Q7 is connected to the second latched node 106 within latch 102.
The first latched node 104 of the latch 102 is connected to the input of a first CMOS inverter 108, and the output of the first CMOS inverter 108 is connected to the input of a second CMOS inverter 110. The output of the second CMOS inverter 110 is connected to Vdd through a capacitor C5 and is further connected to the input of a third CMOS inverter 112. The output of the third CMOS inverter 112 is connected to the input of a fourth CMOS inverter 114. The output of the fourth CMOS inverter 114 is connected at feedback node 120 to the gate of transistor Q5 and is further connected to the input of a fifth CMOS inverter 116, whose output provides the power on reset (POR) signal.
The circuit 100 further includes n-channel transistors Q8–Q10. The transistor Q8 is source-drain connected between latched node 104 and Vdd. The gate of transistor Q8 is connected to ground through a capacitor C6, and is connected to both the gate and drain of transistor Q9 and also to the source of transistor Q10. The source of transistor Q9 and the gate and drain of transistor Q10 are connected to Vdd.
The circuit of FIG. 1 is used to generate a single pulse at power on of Vdd. This single pulse can be used in many applications including initializing latches, nodes and kick starting oscillator circuits.
Reference is now additionally made to FIG. 3 wherein there is shown a waveform trace illustrating operation of the circuit of FIG. 1. As Vdd ramps up and exceeds the Vtp level of the latch 102, the latched nodes 104 and 106 assume a certain state relationship. For example, the transistors Q1–Q4 can be dimensioned in such a way as to set latched node 104 low and latched node 106 high as the circuit begins to power up. With latched node 106 high and latched node 104 low, the set of CMOS inverters 108–114 will set feedback node 120 low and thus turn on transistor Q5. Through the CMOS inverter 116, the POR output signal will go high (as shown at reference 130 in FIG. 3). Transistor Q5, which is now on, then fights against turned on transistor Q6 to pull input node 122 high and charge the capacitor C4. When input node 122 then exceeds Vtn as it goes high (following an RC time constant induced delay), transistor Q7 turns on and drags latched node 106 from the high towards the low state. This causes latch 102 to trip and drive latched node 106 low and send latched node 104 high. With latched node 106 low and latched node 104 high, the set of CMOS inverters 108–114 will set feedback node 120 high and thus turn off transistor Q5 (and therefore cut-off the static current flowing through transistors Q5 and Q6 to minimize power drain). Through the CMOS inverter 116, the POR output signal will then go low (as shown at reference 132 in FIG. 3). Input node 122 then returns low and turns off transistor Q7 thus preserving the latched states of the latch 102.
Some companion circuits used with the circuit 100, such as, for example, a low current oscillator, require that the POR signal transition from high to low at about Vdd=1.2 V for the worst case condition (considering process and temperature variation). It is recognized by those skilled in the art that the Vdd voltage level transition point for the POR signal from high to low (reference 132) is dependent on the ratio of transistors Q5 and Q6. In a common application of the circuit 100 of FIG. 1, the ramped-up Vdd voltage level is typically 3.3 V or 5.0 V. Since Vdd has to power up to a minimum of 3.0 V in these technologies, the window to generate the transition of the POR signal (at the trip point, reference 132) by properly setting the ratio of transistors Q5 and Q6 is quite wide. For example, the trip point could be relatively easily set through proper ratio setting anywhere from 1.2 V to 2.9 V.
A problem, however, arises when the circuit of FIG. 1 is considered for use in a technology wherein Vtn or Vtp voltages are less than 0.5 V and the ramped-up Vdd voltage level is 1.3 V. Operation of the circuit 100 with a ramped-up Vdd voltage of 1.3 V is specifically illustrated in FIG. 3. The window to generate the trip point in this scenario is very tight with respect to Vdd, and more specifically is from the Vtp voltage level to 1.2 V. With the circuit of FIG. 1, however, and given consideration to all process corners and temperature ranges (for example, −40 to +125 degrees Centigrade), it is not possible to generate at trip point (reference 132) at greater than a ramping-up Vdd voltage level of about 0.64 V (which is Vtp plus 150 mV when Vdd is ramped-up to 1.3 V due to transistor voltage linearity). If the companion circuit, such as a low current oscillator, requires that the POR signal transition from high to low at a greater voltage level than 0.64 V, say about Vdd=1.2 V for the worst case condition to kick start the oscillator, then the circuit of FIG. 1 cannot be used.
A need accordingly exists for a POR circuit that solves the foregoing problem. A need also exists for a POR circuit that is suitable for operation with technologies using a ramped-up Vdd voltage of about 1.3 V, and further is capable of having a POR signal trip point from high to low be settable (perhaps selectable) and in particular be capable of being set to about 1.2 V.